DESIGN AND TEST OF A MULTIPLE-VALUED LOGIC CMOS STANDARD CELL LIBRARY
Fortugno, Vincenzo M
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Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, in current mode CMOS technology to compete with and improve upon conventional binary logic in certain target areas. The chosen technology is important to the success of MVL in augmenting and contributing to the semiconductor logic framework. CMOS is the technology selected for the implementation of the MVL standard cell library in this thesis. It is essential that these circuits can coexist with and perform the functions of existing binary logic circuits, the majority of which are fabricated in CMOS. The design and simulation and/or test of a number of multiple-valued logic standard cells are performed to verify the thesis statement. The MVL designs are made up of six basic elements; the switch, constant, current mirror, threshold, summing node and voltage reference circuits. Built upon the these basic components are the MVL operators including the min, max, tsum, literal, complement of literal, cycle, level restorer and t-gate circuits. In addition, the binary- to-quaternary encoder and quaternary-to-binary decoder circuits are designed, further demonstrating the compatibility between MVL and binary logic. Methods are provided for combining the operators and basic components to synthesize functions via existing binary tools and representations; the Karnaugh map and the sum of products form. Each of the circuits are presented with detailed design specifications. All circuits are simulated with HSPICE and the results verifying operation are graphed. Standard cell library VLSI layout diagrams are presented with accompanying descriptions for a subset of the operators and basic elements. Test results confirming the basic functionality of the fabricated standard cell circuits are also presented. The complete design of two implementations of a quaternary full adder are developed and simulated to reveal optional design methodologies available in MVL, and to confirm the validity of the application of MVL design for realizing functions.