DESIGN AND IMPLEMENTATION OF A VLSI SYSTOLIC ARRAY FOR THE TRANSPORTATION SIMPLEX ALGORITHM
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The increasing demand for high speed and improved performance in modern signal and image processing applications, and the availability of low-cost, high-density, high-speed VLSI devices have facilitated the design and implementation of massively parallel processors. The decreasing hardware cost and the emerging computer-aided design facilities have inspired many innovative designs in array processor architecture. One of the important advances in array processor architecture is the "systolic architecture". In this thesis, a design of a systolic array for the transportation simplex algorithm is proposed. The transportation problem is one of the most important linear programming problems. It is a general problem of allocating limited resources among competing activities in an optimal way. A basic systolic cell design for the transportation matrix array of size n x m is presented. A simulator for the transportation simplex algorithm was written to verify the proposed design and architecture. The initial basic feasible solution was obtained using Russell's approximation method. Another algorithm to obtain the initial basic feasible solution to the transportation problem based on the "greedy" approach is proposed. The hardware implementation of the basic cell was carried out using the QUISC silicon compiler and the associated standard cell library. The fabricated chips were found to be operational as expected at a maximum operational speed of 10 MHz.