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dc.contributor.advisorBolton, R. J.
dc.creatorLau, Amy Sze Ming
dc.date.accessioned2018-12-20T21:15:50Z
dc.date.available2018-12-20T21:15:50Z
dc.date.issued1990-08
dc.date.submittedAugust 1990en_US
dc.identifier.urihttp://hdl.handle.net/10388/11688
dc.description.abstractDesign rules in an integrated circuit layout are a set of constraints on the feature size and dimensional relationships between different layers of materials used to fabricate the circuit. Most design rule checking is done by running batch jobs on large computer systems. By using special hardware, the speed of the integrated circuit design rule checking can be increased significantly. A hardware design rule checker (DRC) is investigated and developed in this research. The hardware DRC prototype implements an existing design rule checking algorithm (GAP-Geometry Analysis Program) using the TMS34010 gaphics system processor. GAP is a program for checking design rules with just two geometric primitives, and is able to identify the edges which cause a rule violation. The TMS34010 is an advanced 32-bit microprocessor which is optimized for graphics systems. It provides powerful graphics functions, Boolean pixel block transfers and bit-mapped graphics which are suitable for this application. The research is a combination of custom written software that conducts six categories of design rules and additional hardware for optimization of performance. Design rule checking using the Northern Telecom CMOS3 technology has been implemented. Standard cells from the QUISC library were used to verify the hardware DRC.en_US
dc.titleAN INVESTIGATION OF INTEGRATED CIRCUIT HARDWARE DESIGN RULE CHECKING USING THE TMS34010en_US
thesis.degree.departmentElectrical and Computer Engineeringen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Saskatchewanen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science (M.Sc.)en_US
dc.type.genreThesisen_US


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