High-Level Simulation of Multiple-Valued Logic Systems
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Over the past two decades, researchers have proposed a variety of circuits to implement Multiple-Valued Logic (MVL). These circuits were normally verified with PICE or similar circuit simulators. This kind of simulator provides an accurate result but is very time consuming. This thesis presents a VHDL package and cell library for high-level simulation multiple-valued Current-Mode CMOS Logic (CMCL) design. Structural descriptions of a multiple-valued CMCL design basedon this VHDL package and cell library re synthesizable by using binary logic synthesizers. Logic levels in a multiple-valued MCL system are represented in terms of current values. Conventional binary logic gates are also used inside the circuits to generate control signals for switches or outside the circuits to interface with binary logic circuits. Therefore,a VHDL package r multiple-valued CMCL must have the ability to handle both MVL current signals and binary voltage signals. An approach to estimate transistor sizes of CMCL building elements was also eveloped so as to reduce short-channel effects. Some of the conventional multiplealued CMCL operators were revised and verified with HSPICE simulation by using Northern Telecom 0.811 BiCMOS parameters. As well, sequential CMCL circuits such s current multiplexer, quantizer, and quaternary latch were examined. By using t e sequential CMCL circuits and the concept of Dynamic Current Mirror (DCAf) a quaternary CMCL counter cell was designed.