|dc.description.abstract||With the decreasing feature size of ICs, it tends to be more and more sensitive to Single Event Effect (SEE) due to the correspondingly decreasing critical charge. It is significant to evaluate the SEE performance of new technologies and commercial devices, which can provide reference data for the application or hardening design. In this work, the SEE of a common kind of commercial device, SSD and that of a kind of new technology, ST 28nm FDSOI, will be evaluated.
Solid-state drives (SSDs) are widely used in servers, desktops, and portables as storage devices due to their high accessing speed and the anti-vibration performance. Since all of these computing systems carry out critical tasks on a routine basis, it is important to evaluate their single-event (SE) performance to ensure reliability specifications are met by the final product. In this work, two vendors of SSDs were evaluated using alpha particle, pulsed laser, collimated protons and white light neutrons in TRIUMF. The results showed that the micro-controller chip is the most sensitive IC on both vendors of the SSDs. The FIT (Failure In Time. It means 1 error in 109 hours. It has no unit) rate of the micro-controller dominated the FIT rate of the whole SSD. The buffer IC is also sensitive to protons but the FIT rate is much lower than that for the controller. The flash and voltage regulator ICs are also sensitive to protons, but the FIT rates are the lowest amongst the components in the SSDs.
ST Microelectronics’ (STM) 28-nm Ultra-Thin Body and BOX FDSOI technology has shown robust SEE hardening performance compared to those of 28-nm bulk technologies due to the buried oxide layer (SiO2) between the top transistors and substrate. A triple-modular-redundancy (TMR) SRAM was designed as the embedded high-speed memory for radiation-tolerant ARM processors with STM 28nm FDSOI technology. The single event upset cross-section of the SRAM was tested by using heavy ions with LET=15.0 MeV.cm2.mg-1 in both non-TMR and TMR modes with different accumulated fluence. The SRAM cell was also simulated by using the Cogenda TCAD simulation suite and the cross-section was calculated by using the analytic method. The results showed the cross-section is around 2E-10 cm2/bit in non-TMR mode, and in TMR mode it varied from one to several orders lower than the non-TMR mode according to the specifically accumulated fluence. As a scrubbing circuit was designed to reduce the accumulated number of SEUs in the SRAM, the cross-section could be low to 5E-17 cm2/bit, which contributes only negligible errors to the whole system.||