Show simple item record

dc.contributor.advisorKo, Seok-Bum
dc.creatorAdams, Lizzie M
dc.date.accessioned2021-03-16T21:06:00Z
dc.date.available2021-03-16T21:06:00Z
dc.date.created2020-12
dc.date.issued2021-03-16
dc.date.submittedDecember 2020
dc.identifier.urihttp://hdl.handle.net/10388/13288
dc.description.abstractAn application that can produce a useful result despite some level of computational error is said to be error resilient. Approximate computing can be applied to error resilient applications by intentionally introducing error to the computation in order to improve performance, and it has been shown that approximation is especially well-suited for application in arithmetic computing hardware. In this thesis, novel approximate arithmetic architectures are proposed for three different operations, namely multiplication, division, and the multiply accumulate (MAC) operation. For all designs, accuracy is evaluated in terms of mean relative error distance (MRED) and normalized mean error distance (NMED), while hardware performance is reported in terms of critical path delay, area, and power consumption. Three approximate Booth multipliers (ABM-M1, ABM-M2, ABM-M3) are designed in which two novel inexact partial product generators are used to reduce the dimensions of the partial product matrix. The proposed multipliers are compared to other state-of-the-art designs in terms of both accuracy and hardware performance, and are found to reduce power consumption by up to 56% when compared to the exact multiplier. The function of the multipliers is verified in several image processing applications. Two approximate restoring dividers (AXRD-M1, AXRD-M2) are proposed along with a novel inexact restoring divider cell. In the first divider, the conventional cells are replaced with the proposed inexact cells in several columns. The second divider computes only a subset of the trial subtractions, after which the divisor and partial remainder are rounded and encoded so that they may be used to estimate the remaining quotient bits. The proposed dividers are evaluated for accuracy and hardware performance alongside several benchmarking designs, and their function is verified using change detection and foreground extraction applications. An approximate MAC unit is presented in which the multiplication is implemented using a modified version of ABM-M3. The delay is reduced by using a fused architecture where the accumulator is summed as part of the multiplier compression. The accuracy and hardware savings of the MAC unit are measured against several works from the literature, and the design is utilized in a number of convolution operations.
dc.format.mimetypeapplication/pdf
dc.subjectapproximate computing
dc.subjectcomputer arithmetic
dc.titleImproving the Hardware Performance of Arithmetic Circuits using Approximate Computing
dc.typeThesis
dc.date.updated2021-03-16T21:06:00Z
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorUniversity of Saskatchewan
thesis.degree.levelMasters
thesis.degree.nameMaster of Science (M.Sc.)
dc.type.materialtext
dc.contributor.committeeMemberDinh, Anh
dc.contributor.committeeMemberChen, Li
dc.contributor.committeeMemberSpiteri, Ray
dc.creator.orcid0000-0001-6670-5896


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record