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dc.creatorChen, Mo 1990-
dc.date.accessioned2017-01-23T17:39:51Z
dc.date.available2018-10-16T17:31:21Z
dc.date.created2017-01
dc.date.issued2017-01-23
dc.date.submittedJanuary 2017
dc.identifier.urihttp://hdl.handle.net/10388/7705
dc.description.abstractRadiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A single particle from a radiation environment strikes semiconductor materials resulting in voltage and current perturbation, where errors are induced. This phenomenon is termed a Single Event Effect (SEE). With the shrinking of transistor size, charge sharing between adjacent devices leads to less effectiveness of current radiation hardening methods. Improving fault-tolerance of storage cells and logic gates in advanced technologies becomes urgent and important. A new Single Event Upset (SEU) tolerant latch is proposed based on a previous hardened Quatro design. Soft error analysis tools are used and results show that the critical charge of the proposed design is approximately 2 times higher than that of the reference design with negligible penalty in area, delay, and power consumption. A test chip containing the proposed flip-flop chains was designed and exposed to alpha particles as well as heavy ions. Radiation experimental results indicate that the soft error rates of the proposed design are greatly reduced when Linear Energy Transfer (LET) is lower than 4, which makes it a suitable candidate for ground-level high reliability applications. To improve radiation tolerance of combinational circuits, two combinational logic gates are proposed. One is a layout-based hardening Cascode Voltage Switch Logic (CVSL) and the other is a fault-tolerant differential dynamic logic. Results from a SEE simulation tool indicate that the proposed CVSL has a higher critical charge, less cross section, and shorter Single Event Transient (SET) pulses when compared with reference designs. Simulation results also reveal that the proposed differential dynamic logic significantly reduces the SEU rate compared to traditional dynamic logic, and has a higher critical charge and shorter SET pulses than reference hardened design.
dc.format.mimetypeapplication/pdf
dc.subjectSingle Event Effect
dc.subjectRadiation Resistance
dc.subjectDigital Circuits
dc.subjectDynamic Logic
dc.subjectFlip-flop
dc.subjectCMOS Static Logic
dc.titleSingle Event Effect Hardening Designs in 65nm CMOS Bulk Technology
dc.typeThesis
dc.date.updated2017-01-23T17:39:51Z
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorUniversity of Saskatchewan
thesis.degree.levelMasters
thesis.degree.nameMaster of Science (M.Sc.)
dc.type.materialtext
dc.contributor.committeeMemberBui, Francis
dc.contributor.committeeMemberChung, Chi Yung
dc.contributor.committeeMemberWu, Fangxiang
dc.creator.orcid0000-0002-6279-6556
local.embargo.terms2018-01-23


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