An FPGA-Based 256-QAM Modem with Carrier Recovery
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The ever-increasing demand for more access to digital information has forced data providers and data switching networks to offer higher data rates over the same bandwidth. The implementation of a high performance digital communication system is a significant task. The researcher has developed algorithms and modulation schemes that sustain rates of several megabits per second. However, these algorithms are quite complex and require large digital circuits. Therefore, they are unwieldy for direct digital implementation. In order to alleviate this effect, the researcher has rendered and reorganized these algorithms for effective implementation in order to improve the efficiency, simplicity, scalability, flexibility and gate count of the digital communications system design. In this thesis the proposed design of a high-speed 256-QAM (Quadrature Amplitude Modulation) modem was developed for the effective implementation in FPGAs (Field Programmable Gate Arrays). Although FPGAs are less efficient in terms of the gate count than ASICs (Application Specific Integrated Circuits), their main advantage over ASICs is the in-the-field programming. Therefore, the architectures of FPGAs are designed to be very flexible and reusable. This thesis proposes solutions for efficient multirate pulse shaping and matched filters, the CORDIC (Coordinate Rotation Digital Computer) algorithm and the DPLL (Digital Phase Locked Loop) for carrier recovery.