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      • Electronic Theses and Dissertations
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      • HARVEST
      • College of Graduate and Postdoctoral Studies
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      Implementation of a Low Cost Reconfigurable Transform Architecture for Multiple Video Codecs

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      MARTUZA-THESIS.pdf (1.062Mb)
      Date
      2013-07-29
      Author
      Martuza, Muhammad
      Type
      Thesis
      Degree Level
      Masters
      Metadata
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      Abstract
      Currently different types of transform techniques are used by different video codecs to achieve data compression during video frame transmission. Among them, Discrete Cosine Transform (DCT) is supported by most of modern video standards. The integer DCT (Int-DCT) is an integer approximation of DCT. It can be implemented exclusively with integer arithmetic. Int-DCT proves to be highly advantageous in cost and speed for hardware implementations. In particular, the 4x4 and 8x8 block size Int-DCTs have the increased applicability at the current multimedia industry because of their simpler implementation and better de-correlation performance for high definition (HD) video signals. In this thesis, we present a fast and cost-shared reconfigurable architecture to compute variable block size Int-DCT for four modern video codecs – AVS, H.264/AVC, VC-1 and HEVC (under development). Based on the symmetric structure of the transform matrices and the similarity in matrix operations, we have developed a generalized “decompose and share” algorithm to compute the 4x4 and 8x8 block size Int-DCT. The algorithm is later applied to those four video codecs. Our shared hardware approach ensures the maximum circuit reuse during the computation. The entire architecture is multiplier free and designed with only adders and shifters to minimize hardware cost and improve working frequency. Finally, the design is implemented on a FPGA and later synthesized in CMOS 0.18um technology to compare the cost and performance with existing designs. The results show significant reduction in hardware cost and meet the requirements of real time video coding applications.
      Degree
      Master of Science (M.Sc.)
      Department
      Electrical and Computer Engineering
      Program
      Electrical Engineering
      Supervisor
      Wahid, Khan A.; MacCrosky, Carl D.
      Committee
      Chowdhury, Nurul A.; Bui, Francis M.; Odeshi, Akindele G.
      Copyright Date
      June 2012
      URI
      http://hdl.handle.net/10388/ETD-2012-06-472
      Subject
      Video codecs, HEVC, AVS, H.264, VC-1, 4x4 IDCT, 8x8 IDCT, Multiple transform unit, Reconfigurable Architecture, Low cost design
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      • Electronic Theses and Dissertations
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