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dc.contributor.advisorTeng, Hsiang-Yung (Daniel)en_US
dc.creatorHu, Songen_US
dc.date.accessioned2007-04-05T13:32:11Zen_US
dc.date.accessioned2013-01-04T04:28:13Z
dc.date.available2007-04-09T08:00:00Zen_US
dc.date.available2013-01-04T04:28:13Z
dc.date.created2007-04en_US
dc.date.issued2007-04-09en_US
dc.date.submittedApril 2007en_US
dc.identifier.urihttp://hdl.handle.net/10388/etd-04052007-133211en_US
dc.description.abstractQuadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.en_US
dc.language.isoen_USen_US
dc.subjectCMOS integrated circuitsen_US
dc.subjectquadrature modulatoren_US
dc.subjectlow-poweren_US
dc.titleA low-power quadrature digital modulator in 0.18um CMOSen_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Saskatchewanen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science (M.Sc.)en_US
dc.type.materialtexten_US
dc.type.genreThesisen_US
dc.contributor.committeeMemberSaadat Mehr, Aryanen_US
dc.contributor.committeeMemberDinh, Anh vanen_US
dc.contributor.committeeMemberChen, Lien_US
dc.contributor.committeeMemberBurton, Richard T.en_US


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