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      • HARVEST
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      A high performance pseudo-multi-core elliptic curve cryptographic processor over GF(2^163)

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      Date
      2010-04
      Author
      Zhang, Yu
      Type
      Thesis
      Degree Level
      Masters
      Metadata
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      Abstract
      Elliptic curve cryptosystem is one type of public-key system, and it can guarantee the same security level with Rivest, Shamir and Adleman (RSA) with a smaller key size. Therefore, the key of elliptic curve cryptography (ECC) can be more compact, and it brings many advantages such as circuit area, memory requirement, power consumption, performance and bandwidth. However, compared to private key system, like Advanced Encryption Standard (AES), ECC is still much more complicated and computationally intensive. In some real applications, people usually combine private-key system with public-key system to achieve high performance. The ultimate goal of this research is to architect a high performance ECC processor for high performance applications such as network server and cellular sites. In this thesis, a high performance processor for ECC over Galois field (GF)(2^163) by using polynomial presentation is proposed for high-performance applications. It has three finite field (FF) reduced instruction set computer (RISC) cores and a main controller to achieve instruction-level parallelism (ILP) with pipeline so that the largely parallelized algorithm for elliptic curve point multiplication (PM) can be well suited on this platform. Instructions for combined FF operation are proposed to decrease clock cycles in the instruction set. The interconnection among three FF cores and the main controller is obtained by analyzing the data dependency in the parallelized algorithm. Five-stage pipeline is employed in this architecture. Finally, the u-code executed on these three FF cores is manually optimized to save clock cycles. The proposed design can reach 185 MHz with 20; 807 slices when implemented on Xilinx XC4VLX80 FPGA device and 263 MHz with 217,904 gates when synthesized with TSMC .18um CMOS technology. The implementation of the proposed architecture can complete one ECC PM in 1428 cycles, and is 1.3 times faster than the current fastest implementation over GF(2^163) reported in literature while consumes only 14:6% less area on the same FPGA device.
      Degree
      Master of Science (M.Sc.)
      Department
      Electrical Engineering
      Program
      Electrical Engineering
      Supervisor
      Ko, Seok-Bum; Chen, Li
      Committee
      Dinh, Anh v.; Teng, Daniel; Eager, Derek
      Copyright Date
      April 2010
      URI
      http://hdl.handle.net/10388/etd-05032010-135617
      Subject
      polynomial basis
      elliptic curve cryptograhpy
      instruction-level parallelism
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