Show simple item record

dc.contributor.advisorChen, Lien_US
dc.creatorWang, Kuandeen_US
dc.date.accessioned2010-06-30T20:44:01Zen_US
dc.date.accessioned2013-01-04T04:41:26Z
dc.date.available2011-07-15T08:00:00Zen_US
dc.date.available2013-01-04T04:41:26Z
dc.date.created2010-06en_US
dc.date.issued2010-06en_US
dc.date.submittedJune 2010en_US
dc.identifier.urihttp://hdl.handle.net/10388/etd-06302010-204401en_US
dc.description.abstractWith the increment of mobile, biomedical and space applications, digital systems with low-power consumption are required. As a main part in digital systems, low-power memories are especially desired. Reducing the power supply voltages to sub-threshold region is one of the effective approaches for ultra low-power applications. However, the reduced Static Noise Margin (SNM) of Static Random Access Memory (SRAM) imposes great challenges to the subthreshold SRAM design. The conventional 6-transistor SRAM cell does not function properly at sub-threshold supply voltage range because it has no enough noise margin for reliable operation. In order to achieve ultra low-power at sub-threshold operation, previous research work has demonstrated that the read and write decoupled scheme is a good solution to the reduced SNM problem. A Dual Interlocked Storage Cell (DICE) based SRAM cell was proposed to eliminate the drawback of conventional DICE cell during read operation. This cell can mitigate the singleevent effects, improve the stability and also maintain the low-power characteristic of subthreshold SRAM, In order to make the proposed SRAM cell work under different power supply voltages from 0.3 V to 0.6 V, an improved replica sense scheme was applied to produce a reference control signal, with which the optimal read time could be achieved. In this thesis, a 2K ~8 bits SRAM test chip was designed, simulated and fabricated in 90nm CMOS technology provided by ST Microelectronics. Simulation results suggest that the operating frequency at VDD = 0.3 V is up to 4.7 MHz with power dissipation 6.0 ƒÊW, while it is 45.5 MHz at VDD = 0.6 V dissipating 140 ƒÊW. However, the area occupied by a single cell is larger than that by conventional SRAM due to additional transistors used. The main contribution of this thesis project is that we proposed a new design that could simultaneously solve the ultra low-power and radiation-tolerance problem in large capacity memory design.en_US
dc.language.isoen_USen_US
dc.subjectSRAMen_US
dc.subjectSingle event upseten_US
dc.subjectFault-toleranceen_US
dc.subjectSub-thresholden_US
dc.titleUltra low-power fault-tolerant SRAM design in 90nm CMOS technologyen_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Saskatchewanen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science (M.Sc.)en_US
dc.type.materialtexten_US
dc.type.genreThesisen_US
dc.contributor.committeeMemberEager, Dereken_US
dc.contributor.committeeMemberWahid, Khan A.en_US
dc.contributor.committeeMemberKo, Seok-Bumen_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record