Reduction of co-simulation runtime through parallel processing
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Date
2009-08
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Journal Title
Journal ISSN
Volume Title
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ORCID
Type
Degree Level
Masters
Abstract
During the design phase of modern digital and mixed signal devices, simulations are run to determine the fitness of the proposed design. Some of these simulations can take large amounts of time, thus slowing down the time to manufacture of the system prototype. One of the typical simulations that is done is an integration simulation that simulates the hardware and software at the same time. Most simulators used in this task are monolithic simulators. Some simulators do have the ability to have external libraries and simulators interface with it, but the setup can be a tedious task. This thesis proposes, implements and evaluates a distributed simulator called PDQScS, that allows for speed up of the simulation to reduce this bottleneck in the design cycle without the tedious separation and linking by the user. Using multiple processes and SMP machines a simulation run time reduction was found.
Description
Keywords
HW/SW simulation, Parallel computing
Citation
Degree
Master of Science (M.Sc.)
Department
Computer Science
Program
Computer Science