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dc.contributor.advisorTeng, Danielen_US
dc.creatorPourhaj, Peymanen_US
dc.date.accessioned2010-09-13T22:00:22Zen_US
dc.date.accessioned2013-01-04T04:58:18Z
dc.date.available2011-10-04T08:00:00Zen_US
dc.date.available2013-01-04T04:58:18Z
dc.date.created2010-09en_US
dc.date.issued2010-09en_US
dc.date.submittedSeptember 2010en_US
dc.identifier.urihttp://hdl.handle.net/10388/etd-09132010-220022en_US
dc.description.abstractDifficulties and dangers in doing experiments on living systems and providing a testbed for theorists make the biologically detailed neural simulation an essential part of neurobiology. Due to the complexity of the neural systems and dynamic properties of the neurons simulation of biologically realistic models is very challenging area. Currently all general purpose simulator are software based. Limitation on the available processing power provides a huge gap between the maximum practical simulation size and human brain simulation as the most complex neural system. This thesis aimed at providing a hardware friendly parallel architecture in order to accelerate the simulation process. This thesis presents a scalable hierarchical architecture for accelerating simulations of large-scale biological neural systems on field-programmable gate arrays (FPGAs). The architecture provides a high degree of flexibility to optimize the parallelization ratio based on available hardware resources and model specifications such as complexity of dendritic trees. The whole design is based on three types of customized processors and a switching module. An addressing scheme is developed which allows flexible integration of various combination of processors. The proposed addressing scheme, design modularity and data process localization allow the whole system to extend over multiple FPGA platforms to simulate a very large biological neural system. In this research Hodgkin-Huxley model is adopted for cell excitability. Passive compartmental approach is used to model dendritic tree with any level of complexity. The whole architecture is verified in MATLAB and all processor modules and the switching unit implemented in Verilog HDL and Schematic Capture. A prototype simulator is integrated and synthesized for Xilinx V5-330t-1 as the target FPGA. While not dependent on particular IP (Intellectual Property) cores, the whole implementation is based on Xilinx IP cores including IEEE-754 64-bit floating-point adder and multiplier cores. The synthesize results and performance analyses are provided.en_US
dc.language.isoen_USen_US
dc.subjectBiological Neuronen_US
dc.subjectSimulationen_US
dc.subjectFPGAen_US
dc.subjectParallel processingen_US
dc.titleScalable parallel architecture for biological neural simulation on hardware platformsen_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Saskatchewanen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Engineering (M.Eng.)en_US
dc.type.materialtexten_US
dc.type.genreThesisen_US
dc.contributor.committeeMemberOsgood, Nathanielen_US
dc.contributor.committeeMemberWahid, Khan A.en_US
dc.contributor.committeeMemberKo, Seok-Bumen_US


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