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dc.creatorJalnapurkar, Anant Dattatrayaen_US
dc.date.accessioned2004-10-21T00:12:41Zen_US
dc.date.accessioned2013-01-04T05:04:05Z
dc.date.available1998-01-01T08:00:00Zen_US
dc.date.available2013-01-04T05:04:05Z
dc.date.created1998-01en_US
dc.date.issued1998-01-01en_US
dc.date.submittedJanuary 1998en_US
dc.identifier.urihttp://hdl.handle.net/10388/etd-10212004-001241en_US
dc.description.abstractSimulation plays an important role in the design of integrated circuits. Due to high costs and large delays involved in their fabrication, simulation is commonly used to verify functionality and to predict performance before fabrication. This thesis describes analysis, implementation and performance evaluation of a distributed memory parallel waveform relaxation technique for the electrical circuit simulation of MOS VLSI circuits. The waveform relaxation technique exhibits inherent parallelism due to the partitioning of a circuit into a number of sub-circuits. These subcircuits can be concurrently simulated on parallel processors. Different forms of parallelism in the direct method and the waveform relaxation technique are studied. An analysis of single queue and distributed queue approaches to implement parallel waveform relaxation on distributed memory machines is performed and their performance implications are studied. The distributed queue approach selected for exploiting the coarse grain parallelism across sub-circuits is described. Parallel waveform relaxation programs based on Gauss-Seidel and Gauss-Jacobi techniques are implemented using a network of eight Transputers. Static and dynamic load balancing strategies are studied. A dynamic load balancing algorithm is developed and implemented. Results of parallel implementation are analyzed to identify sources of bottlenecks. This thesis has demonstrated the applicability of a low cost distributed memory multi-computer system for simulation of MOS VLSI circuits. Speed-up measurements prove that a five times improvement in the speed of calculations can be achieved using a full window parallel Gauss-Jacobi waveform relaxation algorithm. Analysis of overheads shows that load imbalance is the major source of overhead and that the fraction of the computation which must be performed sequentially is very low. Communication overhead depends on the nature of the parallel architecture and the design of communication mechanisms. The run-time environment (parallel processing framework) developed in this research exploits features of the Transputer architecture to reduce the effect of the communication overhead by effectively overlapping computation with communications, and running communications processes at a higher priority. This research will contribute to the development of low cost, high performance workstations for computer-aided design and analysis of VLSI circuits.en_US
dc.language.isoen_USen_US
dc.titleCircuit simulation using distributed waveform relaxation techniquesen_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Saskatchewanen_US
thesis.degree.levelDoctoralen_US
thesis.degree.nameDoctor of Philosophy (Ph.D.)en_US
dc.type.materialtexten_US
dc.type.genreThesisen_US
dc.contributor.committeeMemberWood, Hugh C.en_US
dc.contributor.committeeMemberMcCrosky, Carlen_US


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