A microprocessor-based system for protecting busbars
Gill, Harjeet Singh
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Advancements in digital technology have led to the development of microprocessor-based relays. However, most of these relays use algorithms similar in principle to their electromechanical counterparts. Also, busbar protection using microprocessor-based relays has not received adequate attention unlike other power system components. Few algorithms proposed for protecting busbars lack inherent immunity to current transformer (ct) saturation. They achieve stability by using additional measures, such as, using special circuitry, multiple algorithms and changing the restraint factor, which are not likely to be effective during severe ct saturation. The impact of ct ratio-mismatch is countered by using percentage-bias characteristics that reduces the sensitivity of the relay. This thesis presents a new technique for protecting busbars. The technique uses positive-sequence and negative-sequence models of the power system in a fault-detection algorithm. While phase voltages and currents are used to detect faults, parameters of the power system are not used. Only the arguments of the positive-sequence and negative-sequence impedances computed by the relay are used to make trip decisions. The performance of the technique was investigated for a variety of operating conditions and for several busbar configurations. Data generated by empty simulations of model power systems were used in the investigations. The results verify that the proposed technique is able to distinguish faults in a busbar protection zone from those outside the zone correctly. Additionally, its stability during ct saturation, immunity to ct ratio-mismatch and applicability, without any modifications, to busbars of different configurations have been established. An analysis of the performance of the proposed technique during ct saturation and ratio-mismatch conditions is presented. The effect of various parameters, such as, presence of d.c. offset in the currents, mild and severe saturation of the cts, different sampling frequencies and the impact of the size of data-windows on the estimates of the current phasors have been included. The analysis indicates that the technique is stable during ct saturation and inherently immune to ct ratio-mismatch. The proposed technique was implemented using a general purpose relay hardware. The hardware and software constituents of the prototype, the procedure for testing these relays by using a playback simulator and selected test results are presented in this thesis.