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dc.contributor.advisorNguyen, Haen_US
dc.creatorDuong, Quang Xuanen_US
dc.date.accessioned2010-11-29T16:03:33Zen_US
dc.date.accessioned2013-01-04T05:09:19Z
dc.date.available2011-11-29T08:00:00Zen_US
dc.date.available2013-01-04T05:09:19Z
dc.date.created2010-11en_US
dc.date.issued2010-11en_US
dc.date.submittedNovember 2010en_US
dc.identifier.urihttp://hdl.handle.net/10388/etd-11292010-160333en_US
dc.description.abstractDigital resampling is a process that converts a digital signal from one sampling rate to another. This process is performed by means of interpolating between the input samples to produce output samples at an output sampling rate. The digital interpolation process is accomplished with an interpolation filter. The problem of resampling digital signals at an output sampling rate that is incommensurate with the input sampling rate is the first topic of this thesis. This problem is often encountered in practice, for example in multiplexing video signals from different sources for the purpose of distribution. There are basically two approaches to resample the signals. Both approaches are thoroughly described and practical circuits for hardware implementation are provided. A comparison of the two circuits shows that one circuit requires a division to compute the new sampling times. This time scaling operation adds complexity to the implementation with no performance advantage over the other circuit, and makes the 'division free' circuit the preferred one for resampling. The second topic of this thesis is performance analysis of interpolation filters for Quadrature Amplitude Modulation (QAM) signals in the context of timing recovery. The performance criterion of interest is Modulation Error Ratio (MER), which is considered to be a very useful indicator of the quality of modulated signals in QAM systems. The methodology of digital resampling in hardware is employed to describe timing recovery circuits and propose an approach to evaluate the performance of interpolation filters. A MER performance analysis circuit is then devised. The circuit is simulated with MATLAB/Simulink as well as implemented in Field Programmable Gate Array (FPGA). Excellent agreement between results obtained from simulation and hardware implementation proves the validity of the methodology and practical application of the research works.en_US
dc.language.isoen_USen_US
dc.subjectDigital Resamplingen_US
dc.subjectTiming Recoveryen_US
dc.subjectQAM systemsen_US
dc.titleDigital resampling and timing recovery in QAM systemsen_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Saskatchewanen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science (M.Sc.)en_US
dc.type.materialtexten_US
dc.type.genreThesisen_US
dc.contributor.committeeMemberKoustov, Sashaen_US
dc.contributor.committeeMemberWahid, Khanen_US
dc.contributor.committeeMemberSalt, Ericen_US


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