Show simple item record

dc.contributor.advisorDodds, D. E.en_US
dc.creatorBree, Michael Arthuren_US
dc.date.accessioned2010-12-16T08:19:20Zen_US
dc.date.accessioned2013-01-04T05:10:39Z
dc.date.available2011-12-22T08:00:00Zen_US
dc.date.available2013-01-04T05:10:39Z
dc.date.created1988en_US
dc.date.issued1988en_US
dc.date.submitted1988en_US
dc.identifier.urihttp://hdl.handle.net/10388/etd-12162010-081920en_US
dc.description.abstractThe Viterbi algorithm is used for Forward Error Control (FEC) in systems such as satellite communication. Smaller networks are now utilizing satellite technology, which has created a demand for low cost, moderate speed Viterbi Decoders. Many low cost VLSI Viterbi decoders use bit parallel, sequential node processing techniques. In this thesis, bit-serial techniques are applied which reduce circuit size and allow for a parallel node processing implementation. The use of bit-serial communication paths between circuits also reduces wiring area requirements when compared with bit-­parallel busses. Off-chip wiring of the processing trellis allows multiple chips to be cascaded, thus increasing decoder constraint length and bit-error correction capability. A technique is presented which pairs the node processing circuits and further reduces the number of I/O pins and wires. VLSI chips were designed using the QUISC silicon compiler and associated standard cell library. A single chip can implement constraint length K=4 and will support eight level soft decision and code rates of R=1/2 and R=1/3. A Viterbi algorithm simulator, VSIM, was written to aid in the design and debugging of the chip. The simulator can also be used to predict the performance of various decoder configurations of cascaded chips. Fabricated chips were found to operate as expected at decoded data rates up to 287 kbps. Simulations indicate coding gains ranging from 3.8 dB to 5.2 dB at a decoded bit-error-rate of 10-5.en_US
dc.language.isoen_USen_US
dc.titleA Bit-serial Viterbi processoren_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorUniversity of Saskatchewanen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science (M.Sc.)en_US
dc.type.materialtexten_US
dc.type.genreThesisen_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record