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Multiple-Valued Logic Design in Current-Mode CMOS



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Over the last two decades, design using Multiple-Valued Logic (MVL) has been receiving considerable attention. With recent advancements in processing technologies it is now possible to implement higher-radix functions. MVL circuits have shown the potential of improving the use of chip area through increased functional density and reduced requirements for interconnection wiring. Currently, it is advantageous if MVL circuits are used along with binary circuits in the design of Very Large Scale Integration (VLSI) circuits. In order to minimize the fabrication process related overheads, it is desirable to design MVL circuits that can coexist on the same chip with binary logic circuits. This thesis considers MVL design in current-mode CMOS compatible with existing binary logic CMOS fabrication processes. A given MVL function can be realized in the sum-of-product (SOP) form. The realization cost, in terms of the number of required product terms (PTs) and hence the circuit area, depends on the set of operators used. The choice of the set of operators is technology dependent. A new set of operators, consisting of literal, cycle, complement of literal, complement of cycle, min, and tsum operators is proposed in this thesis. A general structure has been identified for realizing MVL circuits in currentmode CMOS. The structure consists of input, control, and output blocks. The input and the output blocks deal primarily with multiple-valued current signals. The control block signals are binary voltage signals providing flexibility by allowing the use of arbitrarily complex binary circuits. MVL circuits have been designed for the new set of operators using the general structure. The cost, in terms of number of transistors, of realizing the new set of operators and that of each of the existing sets of operators is comparable. The functionality of the designed circuits has been verified for 4-valued logic using HSPICE transient analysis simulations. MVL function realizations using the new set of operators requires fewer PTs compared to realizations based on the existing sets of operators. A comprehensive comparison has been conducted for all 19683 3-valued 2-variable functions. The maximum number of PTs is reduced from 6, using the existing set of operators, to 3, using the new set of operators. The average number of PTs is decreased from 3.61 to 2.61. Sample 4-valued 2-variable function realizations using the new set of operators have also shown similar improvements. In the past, several heuristic-based programs have been reported to obtain an efficient SOP expression for a given MVL function. HAMLET is one of these programs. It accepts user specified function expression and minimizes this expression. It includes implementation of many earlier reported heuristic-based algorithms. The Gold heuristic chooses the best realization after applying all other heuristics implemented in HAMLET. A new heuristic-based synthesis program has been developed to obtain a SOP expression for a given MVL function using the proposed set of operators. For a random sample of 4-valued 2-variable functions, the realizations have been compared for the developed program and the existing program, HAMLET (Gold). It is observed that for 69% of the functions, the developed program performs better and for 4% of the functions the HAMLET (Gold) realizations are better. The average number of PTs required by the developed program and HAMLET (Gold) are 5.53 and 6.62, respectively. In order to further reduce the number of PTs required for MVL function realizations two new approaches have also been identified. The new approaches are based on difference-of-sum-of-products (DOSOP) and sum-of-terms (SOT) realization of MVL functions. It has been shown that the required number of terms can be reduced in the realization of some MVL functions, using the new approaches, as compared to those obtained using the SOP realization.





Doctor of Philosophy (Ph.D.)


Electrical and Computer Engineering


Electrical Engineering



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