A VITERBI DECODER SUITABLE FOR VLSI IMPLEMENTATION
Date
1986-09
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Degree Level
Masters
Abstract
There appears to be a market for low cost, low data rate private satellite communication networks. These networks require a low cost digital earth station to make them economically viable. One method to lower the cost of the earth station is to use an error control scheme to reduce the power required at the expense of increased bandwidth. This thesis examines forward error control (FEC) techniques that can be used in this environment.
. The main objective of this project is to determine if it is feasible to design a suitable FEC system that can be implemented on a single integrated circuit. This FEC system must handle an information rate of at least 56 Kbps and have a coding gain of greater than 5 dB at a decoded bit error rate of 10-6.
A major portion of the thesis is dedicated to building a suitable information base that can be used to evaluate possible implementations. The thesis presents a possible implementation architecture for a single chip Viterbi FEC system. A portion of the Viterbi decoder circuit is implemented in VLSI and simulated using SPICE to determine the maximum information rate. An estimate is made of the coding gain and the required size of the integrated circuit.
The thesis concludes that it is possible to implement a suitable Viterbi FEC system on a single integrated circuit.
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Degree
Master of Science (M.Sc.)
Department
Electrical Engineering