An Integrated Circuit for ECG Processing
This thesis presents the design of an IC for use in the analysis of electrocardiograms (ECG's). This IC was developed because the pattern recognition technique used in the analysis requires a relatively large amount of computation, and custom hardware designed specifically for these calculations is necessary to achieve the desired ECG analysis speed. In this report, the morphology recognition algorithm, which is based upon the Bhattacharyya distance measure, is explained and then modified into a form suitable for implementation in an IC. The major components of the IC are identified as a square-root extractor, a multiplier, a register file, and a system controller. A circuit description and an IC layout is developed for each of these components. The circuits are developed using two circuit simulation computer programs, SPICE and RNL, whose accuracy is checked by comparing their simulation results to measurements taken from a fabricated circuit. The NETLIST description of the complete IC design is checked through RNL simulation. The resulting design has a computational rate which is 10 to 25 times faster than a design based upon a general purpose microprocessor performing identical computations.
Master of Science (M.Sc.)
Electrical and Computer Engineering