A DSP-Based it/4-DQPSK Modem
| dc.contributor.advisor | Salt, J. E. | |
| dc.creator | Li, Wentao | |
| dc.date.accessioned | 2019-01-16T20:20:17Z | |
| dc.date.available | 2019-01-16T20:20:17Z | |
| dc.date.issued | 1999 | |
| dc.date.submitted | Spring 1999 | en_US |
| dc.description.abstract | A modem method known as 7r/4 offset, differentially encoded quadrature phase shift keying (764-DQPSK) has been adopted for the United States and Japanese digital cellular time division multiple access (TDMA) systems and Personal Communications Systems (PCS). The rationale for such a choice is the high bit rate-bandwidth ratio and its applicability to noncoherent detection. Most current systems are implemented with analog hardware. In the ir/4-DQPSK modem described in this thesis, DSP solutions are employed to process not only the baseband signal but also the intermediate frequency (IF) signal. The DSP technologies used in this modem include (1) Digital Complex Sampling, (2) Polyphase Filters, (3) Canonic Signed Digit Multipliers for FIR Filter, (4) Non-Data- Aided Timing Parameter Estimation, (5) Multirate Signal Processing. With these DSP solutions, various problems in analog and baseband DSP approaches, such as dc offset voltages, dc voltage drifts, analog filter phase distortions, quadrature phase and gain imbalance, and amplifier and mixer nonlinearities, are eliminated and very precise and controllable performance can be achieved without sophisticated compensation techniques. Other advantages of the DSP solutions include the ability to easily program the hardware to accommodate different data rates, modulation formats and filter specifications. The DSP solution is also an efficient method to minimize power consumption, size and cost of the systems. The mathematical model, simulation results, hardware designs in Very High Speed Integrated Circuit Hardware Description Language (VHDL), and testing results are presented in this thesis. The DSP-based ,t/4-DQPSK modem is designed and implemented on two Altera FLEX10K70 chips. The chip size is 4,428 logical cells (approximately 82k gates). The maximum bit rate is 5Mbit/sec. For an additive white Gaussian noise channel, the results of a bit error rate (BER) measurement indicate that the BER performance of the modem degrades about 1.5 dB from theory when 17th-order square root raised cosine matched filters are used. The performance degradation due to a carrier frequency offset is also investigated in terms of the BER. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10388/11727 | |
| dc.title | A DSP-Based it/4-DQPSK Modem | en_US |
| dc.type.genre | Thesis | en_US |
| thesis.degree.department | Electrical and Computer Engineering | en_US |
| thesis.degree.discipline | Electrical Engineering | en_US |
| thesis.degree.grantor | University of Saskatchewan | en_US |
| thesis.degree.level | Masters | en_US |
| thesis.degree.name | Master of Science (M.Sc.) | en_US |