Hardware implementation of daubechies wavelet transforms using folded AIQ mapping
| dc.contributor.advisor | Wahid, K. | en_US |
| dc.contributor.committeeMember | Eager, D. | en_US |
| dc.contributor.committeeMember | Dinh, A. | en_US |
| dc.contributor.committeeMember | Teng, D. | en_US |
| dc.creator | Islam, Md Ashraful | en_US |
| dc.date.accessioned | 2010-09-12T19:55:19Z | en_US |
| dc.date.accessioned | 2013-01-04T04:58:08Z | |
| dc.date.available | 2011-09-22T08:00:00Z | en_US |
| dc.date.available | 2013-01-04T04:58:08Z | |
| dc.date.created | 2010-08 | en_US |
| dc.date.issued | 2010-08 | en_US |
| dc.date.submitted | August 2010 | en_US |
| dc.description.abstract | The Discrete Wavelet Transform (DWT) is a popular tool in the field of image and video compression applications. Because of its multi-resolution representation capability, the DWT has been used effectively in applications such as transient signal analysis, computer vision, texture analysis, cell detection, and image compression. Daubechies wavelets are one of the popular transforms in the wavelet family. Daubechies filters provide excellent spatial and spectral locality-properties which make them useful in image compression. In this thesis, we present an efficient implementation of a shared hardware core to compute two 8-point Daubechies wavelet transforms. The architecture is based on a new two-level folded mapping technique, an improved version of the Algebraic Integer Quantization (AIQ). The scheme is developed on the factorization and decomposition of the transform coefficients that exploits the symmetrical and wrapping structure of the matrices. The proposed architecture is parallel, pipelined, and multiplexed. Compared to existing designs, the proposed scheme reduces significantly the hardware cost, critical path delay and power consumption with a higher throughput rate. Later, we have briefly presented a new mapping scheme to error-freely compute the Daubechies-8 tap wavelet transform, which is the next transform of Daubechies-6 in the Daubechies wavelet series. The multidimensional technique maps the irrational transformation basis coefficients with integers and results in considerable reduction in hardware and power consumption, and significant improvement in image reconstruction quality. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10388/etd-09122010-195519 | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | folded mapping | en_US |
| dc.subject | Daubechies wavelet | en_US |
| dc.subject | error-free algorithm | en_US |
| dc.subject | algebraic integer quantization. | en_US |
| dc.title | Hardware implementation of daubechies wavelet transforms using folded AIQ mapping | en_US |
| dc.type.genre | Thesis | en_US |
| dc.type.material | text | en_US |
| thesis.degree.department | Electrical Engineering | en_US |
| thesis.degree.discipline | Electrical Engineering | en_US |
| thesis.degree.grantor | University of Saskatchewan | en_US |
| thesis.degree.level | Masters | en_US |
| thesis.degree.name | Master of Science (M.Sc.) | en_US |