Gokaraju, Rama2021-08-032021-072021-08-03July 2021https://hdl.handle.net/10388/13501The speed at which a fault condition on a power system transmission component can be cleared is directly linked to improved equipment lifespan, safety and increased system transient stability. Numerical protection relays, and the subsequent devel- opment of integrated electronic device protection systems (IED) have traditionally operated in the phasor domain, with a minimum latency greater than one half cycle of the power system frequency. During fault, or major disturbances on power system conductors a travelling wave emanates from the line discontinuity, propagating near the velocity of light to each bus connected to the line. The physics of this are well understood, and have been applied in cable discontinuity testing in the communications field1. Translating these events into a robust, reliable and efficient algorithm can provide fault detection with latencies less than one half cycle. IED’s incorporating travelling wave detection have been developed and recently marketed by the power protection industry, which makes the research into a robust algorithm timely. The objective of this research is to further the understanding of the characteristics, performance, and limitations of equivalent algorithms. In this work, the theory of travelling wave detection is implemented in a relay- ing algorithm using a 1 Mega Bit per second sample rate (1 Mbps). The algorithm was developed using a 200 km, 400 kV transmission system, with realistic compo- nents modelling a typical transmission system fed from multiple generating sources. The transmission zone current samples were obtained using realistic CT models, and applied to the relaying algorithm. This algorithm was developed to achieve a number of elements, including: relia- bility within the context of IEEE C37.100, incorporating dependability and security elements, a design to allow hardware implementation and a design to allow parallel operation in real time. The travelling wave fault detection operates within a 2 ms sampling window, and achieves a high degree of security, selectivity and dependabil- ity by implementing detection of faults within a defined protected area, and blocking of trip conditions for faults outside of the defined protected area. Discrimination of fault types is achieved through the Clarke vector space transform. The algorithm’s performance has been validated using a transient based model developed in PSCAD software, with time-stamped values linked to a MATLAB coded algorithm of the relaying elements. The algorithm developed and researched offers promise in numerical protective re- laying. As a stand alone protective algorithm, the increased speed of fault detection can improve fault clearing times. As an adjunct to existing phasor based distance algorithms, a cost effective time domain protection algorithm can improve protec- tive device reliability during cascading events such as line faults during out of step conditions that would otherwise involve greater delay times. The presented algorithm’s nature may lend it to low cost hardware development that can augment existing impedance, or overcurrent protective schemes. Future work with this algorithm, with its validation in stand alone hardware, can allow commu- nication between protective elements at a bus location. Communication standards such as IEC 61850 allow for very low message latencies. This research may lead to an efficient method to improve fault clearing reliability and speed.application/pdfTravelling waveTransmission line relayHigh speed fault clearingThesis2021-08-03