Bolton, R. J.2019-01-232019-01-232003Spring 200http://hdl.handle.net/10388/11803This thesis presents a self-restored current-mode CMOS multiple-valued logic (MVL) design architecture which consists of an input block,a control block, and an output block. A r-valued logic function to be implemented by this architecture is expressed in a sum of r-1 binary logic functions, j•Vj where j is from 0 to r-1. That is, each binary function has an unique value for logic high. The binary logic functions are in sum-of-product (SOP) form, where a product term (PT)consists of multiple and operations on up-literal operators and the sum is an or operation. For a given MVL function, the input block implements up literal operations with current mirrors and thresholds. The control block implements the r-1 binary functions. The control signals from the control block turn on/off switches in the output block to generate the desired output signals directly from the current sources. According to this architecture,the sum operation of the r-1 binary functions is an arithmetic sum and the min operation between j and Vjis implemented by properly connecting outputs of the control block to the switches-no extra transistors are required for these operations in a current-mode design. Also the input block functions as a MVL- binary converter and the control block is a voltage-mode binary logic circuit and therefore, they can be used as interfaces to external binary logic circuits without extra MVL-binary converters. The average transistor count of resulting circuits is 1.1 to 2.5 times smaller than that of other operator-based MVL designs without sacrificing speed and power. Variations to the architecture that make use of the arithmetic sum and diJJin the input block and output blocks can further reduce the circuit size. The self-restored MVL architecture allows MVL synthesis using a binary logic synthesizer. A computer program was developed to work together with a binary logic synthesizer to generates an area-optimized circuit for a given MVL function according to the self-restored MVL design architecture. An additional computer program was also designed to automatically derive equivalent binary logic circuits for a given MVL function for comparison purposes. This thesis also proposes a new VHDL library for high-level simulation of multiple valued Current-Mode CMOS Logic (CMCL) designs supporting faster verification of synthesized results without using a time-consuming circuit simulator such as SPICE or Spectre. The library has basic MVL entities (behavioral), complex MVL entities (behavioral and structural)as well as standard binary logic gates. A bus resolution function working cooperatively with the basic MVL entities allows MVL logic levels (currents)in individual connections to be displayed. Design examples of a quaternary full adder and bit-slice circuit of a transversal matched filter are presented along with both VHDL and circuit simulation results. The design examples verify that the CMCL library allows the VHDL simulation of current-mode CMOS logic using Leapfrog. Spectre was used to confirm that the VHDL simulations were correct. The circuits were also verified by importing the CMCL library into VSS and performing the simulation.Thesis