AN IMPEDANCE RELAY DESIGN AND THE IMPACT OF ANTI-ALIASING FILTERS ON ITS PERFORMANCE
dc.creator | Bimbhra, Amitpal | |
dc.date.accessioned | 2024-04-02T19:51:39Z | |
dc.date.available | 2024-04-02T19:51:39Z | |
dc.date.issued | 2004-04 | |
dc.date.submitted | April 2004 | |
dc.description.abstract | Faults occur in power systems because of the failure of insulation and structures. The faults almost always result in the flow of large quantities of currents. Protective relays are used, therefore, for detecting the faults and isolating the faulted section of the system before the damage spreads. Traditionally, electromechanical and static technologies have been used for designing and manufacturing relays. More recently, advancements in the VLSI technology have resulted in the development of microprocessor-based numerical relays. Several algorithms have been proposed in the past, which are suitable for using in numerical relays for detecting the occurrence of faults. The hardware of a numerical relay has several subsystems, such as, analog input subsystem, signal conditioning, digital input and output, digital processor and power supply subsystems. Operating speed and accuracy of numerical relays are of major concern. Numerical relays use digital processors to implement protection algorithm. The limited power of the processors can limit the speed of operation of the relay. The speed of operation of the numerical relay also depends on the components of the analog input subsystem, such as, the characteristics of the anti-aliasing filters and the analog-to-digital converters (ADCs). This thesis is concerned with the selection of the specialized digital processors for implementing the Discrete Fourier Transform ,(DFT) algorithm at different sampling frequencies, and the selection of suitable components for the analog input subsystem. The processors were selected based on the computational requirements of the DFT at different sampling frequencies. The filters were designed and simulation tests conducted to evaluate the group delay associated with them at different sampling frequencies. The ADC selection was based on the highest sampling rate it could support. Based on the selection of the digital processors and the ADC; suitable numerical relay hardware was purchased and a numerical distance relay was developed. | |
dc.identifier.uri | https://hdl.handle.net/10388/15556 | |
dc.title | AN IMPEDANCE RELAY DESIGN AND THE IMPACT OF ANTI-ALIASING FILTERS ON ITS PERFORMANCE | |
dc.type.genre | Thesis | |
thesis.degree.department | Electrical Engineering | |
thesis.degree.grantor | University of Saskatchewan | en_US |
thesis.degree.level | Masters | |
thesis.degree.name | Master of Science (M.Sc.) |