High Speed Digital Distance Relaying Scheme for Extra High Voltage Transmission Lines

Abstract

Fast load growth, combined with economic and environmental limitations, has pushed modern power systems to reduce redundancy and operate close to the security limits. Fast and reliable protective relays are needed to prevent stability problems. Full-cycle Fourier and cosine phasor filtering systems are typical implementations of numerical distance relays with a response time of close to one cycle. Fast sub-cycle numerical distance elements are in need, especially for EHV/UHV transmission systems (400 kV and above). For every one millisecond saved in fault clearing time, the stability limit of the transmission system can go up by 15 MW. Even for order generation relays, half-cycle tripping speed is the desirable goal, making an overall clearing time of two and a half cycles. Fast sub-cycle numerical relaying methods such as half-cycle Fourier method, Phaselets, least squares, travelling wave, and wavelet-based methods have been proposed in the literature.

In this thesis, a novel Phaselet-based distance relaying method is proposed by taking into account not only the magnitude errors but also the phase angle errors. The mathematical model for both types of errors is developed. The standard deviations are obtained using a mathematical equation for the magnitude errors and a numerical solution for the phase angle errors. A unique adaptive Mho characteristic is designed according to the standard deviation of the phase angle errors, in addition to the standard deviation of the magnitude errors. The inclusion of the phase angle estimation errors significantly improves relaying security compared to previous methods that didn't consider phase angle errors. The test results show that the operation speed is between 0.62 and 0.85 cycles, which is about 0.15 cycles faster than other sub-cycle distance relaying methods. The achieved tripping speed is similar to solid-state relays. The proposed method has good toleration for CT saturation and CCVT transients errors while maintaining reliable trip decisions. When series compensation is presented, the proposed algorithm can maintain high speed and reliable operation with a reduced Zone 1 configuration.

A second sub-cycle relaying algorithm is proposed based on incremental phasors (IncP). The main novelty of this method is that IncPs are calculated out of Phaselets in the frequency domain, versus conventional incremental quantities are calculated based on either instantaneous sample values in the time domain or FCDFT in the frequency domain. As phasors are readily available after the first proposed Phaselet algorithm, incremental phasors can be calculated by subtracting the steady-state phasor from the latest phasor. A fault within Zone 1 can be detected by comparing the voltage IncP with the pre-fault voltage phasor at Zone 1 boundary. Phase selection is achieved through three deliberately constructed scalar products using IncP. The test results show that the proposed IncP algorithm achieves an operation speed between 0.64 to 0.77 cycles, which is around 0.13 cycles faster than other sub-cycle algorithms. This speed advantage is particularly noticeable for phase-to-phase faults. The proposed algorithm shows a 100% phase selection accuracy, 98% relay dependability and 100% relay security.

Both proposed algorithms are implemented on a Xilinx Field Programmable Gate Arrays (FPGA) board. The developed FPGA relay only takes 4 us to process each input sample set. This high-speed performance can be attributed to the massive hardware parallelism and deep pipelining employed in the design, especially in the finite state machine. FPGA relay breaks the paradigm of sequential execution on digital signal processors (DSP) based digital relays. Ethernet-based substation communication protocols, IEC 61850 Sampled Value (SV) and Generic Object Oriented Substation Events (GOOSE) protocols, are implemented on the same FPGA board. They are used to verify the realistic performance of the proposed algorithms in digital substation environments. This is the first time to report IEC 61850 SV subscriber implementation, along with IEC 61850 GOOSE implementation, on FPGA. It possesses significant practical values. The FPGA prototype is validated on a hardware-in-the-loop platform with a real time digital simulator (RTDS).