Investigation of a 900 MHz CMOS Fractional-N Phase- Locked Loop Based Frequency Synthesizer
Date
1999
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Masters
Abstract
The rising demand for radio frequency (RF) communication system products and the improvement of many aspects of CMOS technology have been the main drivers for the desire to implement the RF transmitter/receiver circuit with a higher level of integration. One of the important blocks in the RF transmitter/receiver is the frequency synthesizer, which is responsible for generating a local oscillator signal for the modulation/demodulation process. The circuit topology most suitable for its implementation is the fractional-N phase-locked loop (PLL).
This thesis discusses the principles of the fractional-N PLL-based frequency synthesizer (fractional-N PLL synthesizer), the procedure of designing the fractional-N PLL synthesizer, and the possibility of implementation at 900 MHz using the CMOSIS5 0.5 micron technology. The design chosen for investigation has a frequency step of 0.2 MHz and frequency range of 880 MHz to 920 MHz.
The fractional-N PLL used for the frequency synthesizer is a third-order PLL; however, for design purpose a second-order PLL was used to simplify the calculations, which are done in the frequency domain. The design was then transferred to the time domain where the system level design of the fractional-N PLL synthesizer (time domain, third-order) was done using the Simulink tool in MATLAB. The simulation was run for both small values of N and large values of N. The simulation results show that there are minor differences compare to the calculation (in the s-domain, second order). It is also shown that the fractional-N design affects the output signal generated due to introduction of spurious noise into the voltage controlled oscillator.
The design of the 900 MHz fractional-N PLL synthesizer blocks was performed at the schematic level. Each circuit block has been verified using Spectre, a circuit simulator available in the Cadence design system. The simulation for the entire circuit was not performed due to constraints on available system resources. The fractional-N PLL synthesizer circuit employs 643 active and passive devices and dissipates 17 mW of power, excluding the loop filter. Based upon the results of the investigation, the CMOSIS5 technology appears appropriate to implement the fractional-N PLL synthesizer.
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Degree
Master of Science (M.Sc.)
Department
Electrical Engineering