Study of Layout Techniques in Dynamic Logic Circuitry for Single Event Effect Mitigation
| dc.contributor.advisor | Chen, Li | en_US |
| dc.contributor.committeeMember | Deters, Ralph | en_US |
| dc.contributor.committeeMember | Dinh, Anh | en_US |
| dc.contributor.committeeMember | Wahid, Khan | en_US |
| dc.creator | Li, Mulong | en_US |
| dc.date.accessioned | 2015-10-07T12:00:22Z | |
| dc.date.available | 2015-10-07T12:00:22Z | |
| dc.date.created | 2015-09 | en_US |
| dc.date.issued | 2015-09-30 | en_US |
| dc.date.submitted | September 2015 | en_US |
| dc.description.abstract | Dynamic logic circuits are highly suitable for high-speed applications, considering the fact that they have a smaller area and faster transition. However, their application in space or other radiation-rich environments has been significantly inhibited by their susceptibility to radiation effects. This work begins with the basic operations of dynamic logic circuits, elaborates upon the physics underlying their radiation vulnerability, and evaluates three techniques that harden dynamic logic from the layout: drain extension, pulse quenching, and a proposed method. The drain extension method adds an extra drain to the sensitive node in order to improve charge sharing, the pulse quenching scheme utilizes charge sharing by duplicating a component that offsets the transient pulse, and the proposed technique takes advantage of both. Domino buffers designed using these three techniques, along with a conventional design as reference, were modeled and simulated using a 3D TCAD tool. Simulation results confirm a significant reduction of soft error rate in the proposed technique and suggest a greater reduction with angled incidence. A 130 nm chip containing designed buffer and register chains was fabricated and tested with heavy ion irradiation. According to the experiment results, the proposed design achieved 30% soft error rate reduction, with 19%, 20%, and 10% overhead in speed, power, and area, respectively. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10388/ETD-2015-09-2253 | en_US |
| dc.language.iso | eng | en_US |
| dc.subject | dynamic logic | en_US |
| dc.subject | single event effect | en_US |
| dc.subject | pulse quenching | en_US |
| dc.title | Study of Layout Techniques in Dynamic Logic Circuitry for Single Event Effect Mitigation | en_US |
| dc.type.genre | Thesis | en_US |
| dc.type.material | text | en_US |
| thesis.degree.department | Electrical and Computer Engineering | en_US |
| thesis.degree.discipline | Electrical Engineering | en_US |
| thesis.degree.grantor | University of Saskatchewan | en_US |
| thesis.degree.level | Masters | en_US |
| thesis.degree.name | Master of Science (M.Sc.) | en_US |