Comparison of Synchronization Methods for Burst-Mode π/4 DQPSK Demodulators
The "burst-mode" of communications is becoming increasingly prevalent in emerging cost-effective wireless packet data networks. These networks employ various forms of TDMA and TDD techniques and are popular as they require very little overhead in the management of network channel resources. Since multiple users share common frequency channels in time, fast and reliable synchronization on a burst by burst basis in the receiver is critical for maintaining efficient data throughput. An attractive modulation technique ill a burst-mode environment is π/4 DQPSK. Since noncoherent detection may be performed on 1T'/4 DQPSK; synchronization is inherently rapid as only symbol timing information needs to be recovered. Various synchronization techniques are suitable for π/4 DQPSK, but surprisingly little has been published on the performance of these techniques in burst-mode. This research examined the performance of several synchronization techniques in a burst-mode environment. It also compared the digital hardware realizations for various synchronization techniques and explored trade-offs between performance and implementation complexity. A number of synchronization methods were investigated based on some common criteria: cost, complexity and performance. Four methods were chosen and simulated. Each method. was evaluated for application to a burst-mode system. The most viable technique was chosen and a functional π/4 DQPSK demodulator based on the method. was built and tested in the laboratory. The most promising method was found to be the maximum amplitude method. This method proved to be very effective in burst-mode, achieving reliable synchronization in only a few symbols in simulation; The trade-off for this rapid synchronization was some degradation in bit error rate tracking performance. A modification to the maximum amplitude method (named modified maximum amplitude) was proposed and implemented which improved the tracking performance while maintaining rapid synchronization performance. Both methods were suitable for implementation in programmable digital hardware using a complex programmable logic device. Additionally, testing results showed both systems to be very robust as synchronization times were consistent over a wide range of Eb/No.
Master of Science (M.Sc.)
Electrical and Computer Engineering