Study of Single Event Effects on 28nm ARM Core Testing Chip
Date
2019-03-28
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
ORCID
Type
Thesis
Degree Level
Masters
Abstract
With the development of silicon technologies, the minimum feature size of transistors has scaled down to several nanometers. This remarkably increases the number of transistors on a single chip, leads to improved circuit performance and reduced cost. However, Single Event Effects (SEE) induced by energetic particles are more significant for nanometer CMOS technologies due to the reduction in critical charge, higher clock speeds, lower operating voltages and high circuit densities. Research studies have shown that, compared to bulk technologies, silicon on insulator (SOI) technologies reduces the charge collection length of incident ions leading to less collected charge, and thus lower SEE sensitivity. STMicroelectronics' 28-nm fully depleted SOI technology has shown superior performance in terms of single event effects resistance, compared to those of 28-nm bulk technologies. The reduced SEE sensitivity as well as the Single Event Latch-up immunity makes this technology attractive for harsh radiation environments such as space. Previous work has focused on devices or small circuits, however, the overall SEE performance in complex circuits at different operating conditions needs to be further investigated. Microprocessors are widely used in avionics and space applications due to their performance and extensive tool support. It is thus interesting to assess the SEE performance of ARM Cortex-M0 microcontroller cores implemented in the 28-nm FDSOI technology.
In this thesis, the goal is to study signal event effects in a test chip that includes several ARM Cortex-M0 cores designed with different SEE-tolerant levels. The test chip has a triple-module-redundant (TMR) SRAM and an on-chip clock system, which are shared by the ARM cores. The test chip also includes custom-designed SEE-hardened flip-flops and regular flip-flops from the standard cell library, which were connected into two shift-register chains to independently evaluate their SEE performance. A FPGA-based testing system was developed to test the flip-flop chains and ARM cores. The system includes a raspberry Pi board, a daughter card for the test chip, and the FPGA mother board. Eight different microprocessor testing programs were also developed for the ARM cores. Heavy ion experiments were performed with the testing system. Results showed that the hardened flip-flops have excellent performance, which do not have errors up to 42 $MeV \times cm^{2}/mg$ of LET. The SRAM were also tested separately during heavy ion experiments and it showed that the SRAMs without TMR protection are sensitive to SEEs, however, the TMR can effectively protect the SRAM from SEEs. Two ARM Cortex-M0 cores were also evaluated with the heavy ion experiments. The results showed that the ARM core with hardened flip-flops has improved performance compared to the reference core which was implemented with regular cells from the standard library. To the author's knowledge, this is the first published work where two different implementations of the same processor core have been evaluated under heavy ion irradiation.
Description
Keywords
Single Event Effects, ARM, cross-section
Citation
Degree
Master of Science (M.Sc.)
Department
Electrical and Computer Engineering
Program
Electrical Engineering