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Supply Voltage Dependence of Heavy Ion Induced SEEs on 65nm CMOS Bulk SRAMs

dc.contributor.advisorChen, Lien_US
dc.contributor.committeeMemberKarki, Rajeshen_US
dc.contributor.committeeMemberWahid, Khanen_US
dc.contributor.committeeMemberDeters, Ralphen_US
dc.creatorWu, Qiongen_US 2015en_US
dc.description.abstractThe power consumption of Static Random Access Memory (SRAM) has become an important issue for modern integrated circuit design, considering the fact that they occupy large area and consume significant portion of power consumption in modern nanometer chips. SRAM operating in low power supply voltages has become an effective approach in reducing power consumption. Therefore, it is essential to experimentally characterize the single event effects (SEE) of hardened and unhardened SRAM cells to determine their appropriate applications, especially when a low supply voltage is preferred. In this thesis, a SRAM test chip was designed and fabricated with four cell arrays sharing the same peripheral circuits, including two types of unhardened cells (standard 6T and sub-threshold 10T) and two types of hardened cells (Quatro and DICE). The systems for functional and radiation tests were built up with power supply voltages that ranged from near threshold 0.4 V to normal supply 1 V. The test chip was irradiated with alpha particles and heavy ions with various linear energy transfers (LETs) at different core supply voltages, ranging from 1 V to 0.4 V. Experimental results of the alpha test and heavy ion test were consistent with the results of the simulation. The cross sections of 6T and 10T cells present much more significant sensitivities than Quatro and DICE cells for all tested supply voltages and LET. The 10T cell demonstrates a more optimal radiation performance than the 6T cell when LET is small (0.44 MeV·cm2/mg), yet no significant advantage is evident when LET is larger than this. In regards to the Quatro and DICE cells, one does not consistently show superior performance over the other in terms of soft error rates (SERs). Multi-bit upsets (MBUs) occupy a larger portion of total SEUs in DICE cell when relatively larger LET and smaller supply voltage are applied. It explains the loss in radiation tolerance competition with Quatro cell when LET is bigger than 9.1 MeV·cm2/mg and supply voltage is smaller than 0.6 V. In addition, the analysis of test results also demonstrated that the error amount distributions follow a Poisson distribution very well for each type of cell array.en_US
dc.subjectSingle Event Effect SRAM Heavy ion test Supply voltageen_US
dc.titleSupply Voltage Dependence of Heavy Ion Induced SEEs on 65nm CMOS Bulk SRAMsen_US
dc.type.materialtexten_US and Computer Engineeringen_US Engineeringen_US of Saskatchewanen_US of Science (M.Sc.)en_US


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