University of SaskatchewanHARVEST
  • Login
  • Submit Your Work
  • About
    • About HARVEST
    • Guidelines
    • Browse
      • All of HARVEST
      • Communities & Collections
      • By Issue Date
      • Authors
      • Titles
      • Subjects
      • This Collection
      • By Issue Date
      • Authors
      • Titles
      • Subjects
    • My Account
      • Login
      JavaScript is disabled for your browser. Some features of this site may not work without it.
      View Item 
      • HARVEST
      • Electronic Theses and Dissertations
      • Graduate Theses and Dissertations
      • View Item
      • HARVEST
      • Electronic Theses and Dissertations
      • Graduate Theses and Dissertations
      • View Item

      3D-IC Technology Characterization and Test Chip Design

      Thumbnail
      View/Open
      FAN-THESIS.pdf (23.21Mb)
      Date
      2013-08-20
      Author
      Fan, Li
      Type
      Thesis
      Degree Level
      Masters
      Metadata
      Show full item record
      Abstract
      With sub-micron silicon processing technology reaching under 30nm, it becomes more difficult for integrated circuits to achieve higher integration through the scaling down of the transistor size. Three-dimensional integrated circuit (3D-IC) technology stacks multiple dies together and connects them using through-silicon vias (TSVs). This is a low cost and highly efficient way to increase integration. TSVs and stacked dies are two major features of the 3D-IC technology. However, the stacked structures using TSV interconnects induce concerns in reliability such as TSV strain effect, heat problem, and TSV coupling at high frequency, etc. The reliability concerns need to be carefully addressed before 3D-IC technologies can be widely adopted by the industry. Many studies have been carried out in this field, but there has not been much significant work done for testing electrical, mechanical and thermal issues of the 3D-IC technology simultaneously on a single test chip. In this work, a test chip including various test structures was designed to study and analyze these issues in a 3D-IC technology. An accurate resistance and capacitance (RC) model of the TSV for low frequency design was developed, high frequency electrical performance of the TSVs was characterized, coupling between TSVs was modeled, and the stress effect and the heat dissipation method were analyzed in the 3D-IC technology. The TSV model could be added to the design kit for future 3D-IC design and other results could be used to improve the reliability of 3D-IC designs and optimize the performance.
      Degree
      Master of Science (M.Sc.)
      Department
      Electrical and Computer Engineering
      Program
      Electrical Engineering
      Supervisor
      Chen, Li
      Committee
      Ko, Seok-Bum; Gokaraju, Ramakrishna; Wu, Fangxiang
      Copyright Date
      February 2013
      URI
      http://hdl.handle.net/10388/ETD-2013-02-912
      Subject
      3D-IC
      TSV
      Collections
      • Graduate Theses and Dissertations
      University of Saskatchewan

      University Library

      The University of Saskatchewan's main campus is situated on Treaty 6 Territory and the Homeland of the Métis.

      © University of Saskatchewan
      Contact Us | Disclaimer | Privacy