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Reduction of co-simulation runtime through parallel processing

dc.contributor.advisorMakaroff, Dwighten_US
dc.contributor.committeeMemberBolton, Ronen_US
dc.contributor.committeeMemberEager, Dereken_US
dc.contributor.committeeMemberSpiteri, Raymonden_US
dc.creatorCoutu, Jason Deanen_US
dc.date.accessioned2009-09-08T14:00:47Zen_US
dc.date.accessioned2013-01-04T04:56:58Z
dc.date.available2010-09-10T08:00:00Zen_US
dc.date.available2013-01-04T04:56:58Z
dc.date.created2009-08en_US
dc.date.issued2009-08en_US
dc.date.submittedAugust 2009en_US
dc.description.abstractDuring the design phase of modern digital and mixed signal devices, simulations are run to determine the fitness of the proposed design. Some of these simulations can take large amounts of time, thus slowing down the time to manufacture of the system prototype. One of the typical simulations that is done is an integration simulation that simulates the hardware and software at the same time. Most simulators used in this task are monolithic simulators. Some simulators do have the ability to have external libraries and simulators interface with it, but the setup can be a tedious task. This thesis proposes, implements and evaluates a distributed simulator called PDQScS, that allows for speed up of the simulation to reduce this bottleneck in the design cycle without the tedious separation and linking by the user. Using multiple processes and SMP machines a simulation run time reduction was found.en_US
dc.identifier.urihttp://hdl.handle.net/10388/etd-09082009-140047en_US
dc.language.isoen_USen_US
dc.subjectHW/SW simulationen_US
dc.subjectParallel computingen_US
dc.titleReduction of co-simulation runtime through parallel processingen_US
dc.type.genreThesisen_US
dc.type.materialtexten_US
thesis.degree.departmentComputer Scienceen_US
thesis.degree.disciplineComputer Scienceen_US
thesis.degree.grantorUniversity of Saskatchewanen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science (M.Sc.)en_US

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